CLEON  Version 1
Cloud-Offloaded GPS Receiver
hal_pmm.h
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1 
7 #ifndef __HAL_PMM_H__
8 #define __HAL_PMM_H__
9 
10 #define HAL_ENTER_LPM4() __bis_SR_register(LPM4_bits + GIE)
11 
12 void HAL_PMM_Init(void);
13 
15 /*******************************************************************************
16  *
17  * HAL_PMM.h
18  * Power Management Module Library for MSP430F5xx/6xx family
19  *
20  *
21  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
22  *
23  *
24  * Redistribution and use in source and binary forms, with or without
25  * modification, are permitted provided that the following conditions
26  * are met:
27  *
28  * Redistributions of source code must retain the above copyright
29  * notice, this list of conditions and the following disclaimer.
30  *
31  * Redistributions in binary form must reproduce the above copyright
32  * notice, this list of conditions and the following disclaimer in the
33  * documentation and/or other materials provided with the
34  * distribution.
35  *
36  * Neither the name of Texas Instruments Incorporated nor the names of
37  * its contributors may be used to endorse or promote products derived
38  * from this software without specific prior written permission.
39  *
40  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
43  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
44  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
45  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51  *
52  ******************************************************************************/
53 
54 /*******************************************************************************
55  * Macros
56  ******************************************************************************/
57 #define ENABLE_SVSL() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLE; PMMCTL0_H = 0x00; )
58 #define DISABLE_SVSL() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~SVSLE; PMMCTL0_H = 0x00; )
59 #define ENABLE_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVMLE; PMMCTL0_H = 0x00; )
60 #define DISABLE_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~SVMLE; PMMCTL0_H = 0x00; )
61 #define ENABLE_SVSH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHE; PMMCTL0_H = 0x00; )
62 #define DISABLE_SVSH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~SVSHE; PMMCTL0_H = 0x00; )
63 #define ENABLE_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVMHE; PMMCTL0_H = 0x00; )
64 #define DISABLE_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~SVMHE; PMMCTL0_H = 0x00; )
65 #define ENABLE_SVSL_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLE + SVMLE); PMMCTL0_H = 0x00; )
66 #define DISABLE_SVSL_SVML() st(PMMCTL0_H = 0xA5; SVSMLCTL &= ~(SVSLE + SVMLE); PMMCTL0_H = 0x00; )
67 #define ENABLE_SVSH_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHE + SVMHE); PMMCTL0_H = 0x00; )
68 #define DISABLE_SVSH_SVMH() st(PMMCTL0_H = 0xA5; SVSMHCTL &= ~(SVSHE + SVMHE); PMMCTL0_H = 0x00; )
69 
70 #define ENABLE_SVSL_RESET() st(PMMCTL0_H = 0xA5; PMMRIE |= SVSLPE; PMMCTL0_H = 0x00; )
71 #define DISABLE_SVSL_RESET() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVSLPE; PMMCTL0_H = 0x00; )
72 #define ENABLE_SVML_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE |= SVMLIE; PMMCTL0_H = 0x00; )
73 #define DISABLE_SVML_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVMLIE; PMMCTL0_H = 0x00; )
74 #define ENABLE_SVSH_RESET() st(PMMCTL0_H = 0xA5; PMMRIE |= SVSHPE; PMMCTL0_H = 0x00; )
75 #define DISABLE_SVSH_RESET() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVSHPE; PMMCTL0_H = 0x00; )
76 #define ENABLE_SVMH_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE |= SVMHIE; PMMCTL0_H = 0x00; )
77 #define DISABLE_SVMH_INTERRUPT() st(PMMCTL0_H = 0xA5; PMMRIE &= ~SVMHIE; PMMCTL0_H = 0x00; )
78 #define CLEAR_PMM_IFGS() st(PMMCTL0_H = 0xA5; PMMIFG = 0; PMMCTL0_H = 0x00; )
79 
80 // These settings use SVSH/LACE = 0
81 #define SVSL_ENABLED_IN_LPM_FAST_WAKE() st( \
82  PMMCTL0_H = 0xA5; SVSMLCTL |= (SVSLFP + SVSLMD); SVSMLCTL &= ~SVSMLACE; PMMCTL0_H = 0x00; )
83 #define SVSL_ENABLED_IN_LPM_SLOW_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLMD; SVSMLCTL &= \
84  ~(SVSLFP + SVSMLACE); PMMCTL0_H = 0x00; )
85 
86 #define SVSL_DISABLED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= SVSLFP; SVSMLCTL &= \
87  ~(SVSLMD + SVSMLACE); PMMCTL0_H = 0x00; )
88 #define SVSL_DISABLED_IN_LPM_SLOW_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL &= \
89  ~(SVSLFP + SVSMLACE + SVSLMD); PMMCTL0_H = 0x00; )
90 
91 #define SVSH_ENABLED_IN_LPM_NORM_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHMD; SVSMHCTL &= \
92  ~(SVSMHACE + SVSHFP); PMMCTL0_H = 0x00; )
93 #define SVSH_ENABLED_IN_LPM_FULL_PERF() st( \
94  PMMCTL0_H = 0xA5; SVSMHCTL |= (SVSHMD + SVSHFP); SVSMHCTL &= ~SVSMHACE; PMMCTL0_H = 0x00; )
95 
96 #define SVSH_DISABLED_IN_LPM_NORM_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL &= \
97  ~(SVSMHACE + SVSHFP + SVSHMD); PMMCTL0_H = 0x00; )
98 #define SVSH_DISABLED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= SVSHFP; SVSMHCTL &= \
99  ~(SVSMHACE + SVSHMD); PMMCTL0_H = 0x00; )
100 
101 // These setting use SVSH/LACE = 1
102 #define SVSL_OPTIMIZED_IN_LPM_FAST_WAKE() st(PMMCTL0_H = 0xA5; SVSMLCTL |= \
103  (SVSLFP + SVSLMD + SVSMLACE); PMMCTL0_H = 0x00; )
104 #define SVSH_OPTIMIZED_IN_LPM_FULL_PERF() st(PMMCTL0_H = 0xA5; SVSMHCTL |= \
105  (SVSHMD + SVSHFP + SVSMHACE); PMMCTL0_H = 0x00; )
106 
107 /*******************************************************************************
108  * Defines
109  ******************************************************************************/
110 #define PMM_STATUS_OK 0
111 #define PMM_STATUS_ERROR 1
112 
113 /*******************************************************************************
114  * \brief Set Vcore to expected level
115  *
116  * \param level Level to which Vcore needs to be increased/decreased
117  * \return status Success/failure
118  ******************************************************************************/
119 extern uint16_t SetVCore(uint8_t level);
121 
122 #endif