CLEON  Version 1
Cloud-Offloaded GPS Receiver
sys_gps.c
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1 
7 #include "cleon_conf.h"
8 #include "app_define.h"
9 #include "sys_define.h"
10 #include "hal_define.h"
11 #include "fs_define.h"
12 
13 // CLEON data structure
14 extern cleon_header_u uniCLEONHeader;
15 extern cleon_gps_data_u uniCLEONGPSData;
16 extern cleon_sensor_data_u uniCLEONSensorData;
17 
18 // Flags
19 extern bool bFLAG_DMATransferCompleted;
20 
21 /*----------------------------------------------------------------------------*/
29 void SYS_GPS_Init(void)
30 {
31  // Initializing GPS control pins
32  SYS_GPS_InitControlIO();
33 
34  // Stop GPS operation before initialization
35  SYS_GPS_StopOperation();
36 
37  // Program the GPS with pre-configured mode
38  SYS_GPS_InitProgramIO();
39 
40  // Initializing GPS data pins
41  SYS_GPS_InitDataIO();
42 
43 #if GPS_TEST_ON_INITIALIZATION == _ENABLE_
44  // Check if GPS is functional by sampling a chunk of GPS signal and take a look inside
45  for(int i = 1 ; i < MAX_NUMBER_OF_GPS_TEST_COUNT; i++){
46  // If fail, allow more time to settle (100ms, 200ms, 300ms ...)
47  if(SYS_GPS_TestGPS(100 * i) == _SUCCESS_){
48  // Return if it passes GPS test
49  return;
50  }
51  }
52 
53  // If it fails the test, turn LED on
54  GPS_ERROR_LED_ON();
55 #endif
56 }
57 
58 /*----------------------------------------------------------------------------*/
66 void SYS_GPS_InitDataIO(void)
67 {
68  MAX2769_Q0_PORT(OUT) &= ~BV(MAX2769_Q0_1_PIN);
69  MAX2769_Q0_PORT(OUT) &= ~BV(MAX2769_Q0_2_PIN);
70  MAX2769_Q0_PORT(OUT) &= ~BV(MAX2769_Q0_3_PIN);
71  MAX2769_Q0_PORT(OUT) &= ~BV(MAX2769_Q0_4_PIN);
72  MAX2769_Q0_PORT(OUT) &= ~BV(MAX2769_Q0_5_PIN);
73  MAX2769_Q0_PORT(OUT) &= ~BV(MAX2769_Q0_6_PIN);
74  MAX2769_Q0_PORT(OUT) &= ~BV(MAX2769_Q0_7_PIN);
75  MAX2769_Q0_PORT(OUT) &= ~BV(MAX2769_Q0_8_PIN);
76 
77  MAX2769_Q1_PORT(OUT) &= ~BV(MAX2769_Q1_1_PIN);
78  MAX2769_Q1_PORT(OUT) &= ~BV(MAX2769_Q1_2_PIN);
79  MAX2769_Q1_PORT(OUT) &= ~BV(MAX2769_Q1_3_PIN);
80  MAX2769_Q1_PORT(OUT) &= ~BV(MAX2769_Q1_4_PIN);
81  MAX2769_Q1_PORT(OUT) &= ~BV(MAX2769_Q1_5_PIN);
82  MAX2769_Q1_PORT(OUT) &= ~BV(MAX2769_Q1_6_PIN);
83  MAX2769_Q1_PORT(OUT) &= ~BV(MAX2769_Q1_7_PIN);
84  MAX2769_Q1_PORT(OUT) &= ~BV(MAX2769_Q1_8_PIN);
85 
86  MAX2769_I0_PORT(OUT) &= ~BV(MAX2769_I0_1_PIN);
87  MAX2769_I0_PORT(OUT) &= ~BV(MAX2769_I0_2_PIN);
88  MAX2769_I0_PORT(OUT) &= ~BV(MAX2769_I0_3_PIN);
89  MAX2769_I0_PORT(OUT) &= ~BV(MAX2769_I0_4_PIN);
90  MAX2769_I0_PORT(OUT) &= ~BV(MAX2769_I0_5_PIN);
91  MAX2769_I0_PORT(OUT) &= ~BV(MAX2769_I0_6_PIN);
92  MAX2769_I0_PORT(OUT) &= ~BV(MAX2769_I0_7_PIN);
93  MAX2769_I0_PORT(OUT) &= ~BV(MAX2769_I0_8_PIN);
94 
95  MAX2769_I1_PORT(OUT) &= ~BV(MAX2769_I1_1_PIN);
96  MAX2769_I1_PORT(OUT) &= ~BV(MAX2769_I1_2_PIN);
97  MAX2769_I1_PORT(OUT) &= ~BV(MAX2769_I1_3_PIN);
98  MAX2769_I1_PORT(OUT) &= ~BV(MAX2769_I1_4_PIN);
99  MAX2769_I1_PORT(OUT) &= ~BV(MAX2769_I1_5_PIN);
100  MAX2769_I1_PORT(OUT) &= ~BV(MAX2769_I1_6_PIN);
101  MAX2769_I1_PORT(OUT) &= ~BV(MAX2769_I1_7_PIN);
102  MAX2769_I1_PORT(OUT) &= ~BV(MAX2769_I1_8_PIN);
103 
104  MAX2769_Q0_PORT(DIR) &= ~BV(MAX2769_Q0_1_PIN);
105  MAX2769_Q0_PORT(DIR) &= ~BV(MAX2769_Q0_2_PIN);
106  MAX2769_Q0_PORT(DIR) &= ~BV(MAX2769_Q0_3_PIN);
107  MAX2769_Q0_PORT(DIR) &= ~BV(MAX2769_Q0_4_PIN);
108  MAX2769_Q0_PORT(DIR) &= ~BV(MAX2769_Q0_5_PIN);
109  MAX2769_Q0_PORT(DIR) &= ~BV(MAX2769_Q0_6_PIN);
110  MAX2769_Q0_PORT(DIR) &= ~BV(MAX2769_Q0_7_PIN);
111  MAX2769_Q0_PORT(DIR) &= ~BV(MAX2769_Q0_8_PIN);
112 
113  MAX2769_Q1_PORT(DIR) &= ~BV(MAX2769_Q1_1_PIN);
114  MAX2769_Q1_PORT(DIR) &= ~BV(MAX2769_Q1_2_PIN);
115  MAX2769_Q1_PORT(DIR) &= ~BV(MAX2769_Q1_3_PIN);
116  MAX2769_Q1_PORT(DIR) &= ~BV(MAX2769_Q1_4_PIN);
117  MAX2769_Q1_PORT(DIR) &= ~BV(MAX2769_Q1_5_PIN);
118  MAX2769_Q1_PORT(DIR) &= ~BV(MAX2769_Q1_6_PIN);
119  MAX2769_Q1_PORT(DIR) &= ~BV(MAX2769_Q1_7_PIN);
120  MAX2769_Q1_PORT(DIR) &= ~BV(MAX2769_Q1_8_PIN);
121 
122  MAX2769_I0_PORT(DIR) &= ~BV(MAX2769_I0_1_PIN);
123  MAX2769_I0_PORT(DIR) &= ~BV(MAX2769_I0_2_PIN);
124  MAX2769_I0_PORT(DIR) &= ~BV(MAX2769_I0_3_PIN);
125  MAX2769_I0_PORT(DIR) &= ~BV(MAX2769_I0_4_PIN);
126  MAX2769_I0_PORT(DIR) &= ~BV(MAX2769_I0_5_PIN);
127  MAX2769_I0_PORT(DIR) &= ~BV(MAX2769_I0_6_PIN);
128  MAX2769_I0_PORT(DIR) &= ~BV(MAX2769_I0_7_PIN);
129  MAX2769_I0_PORT(DIR) &= ~BV(MAX2769_I0_8_PIN);
130 
131  MAX2769_I1_PORT(DIR) &= ~BV(MAX2769_I1_1_PIN);
132  MAX2769_I1_PORT(DIR) &= ~BV(MAX2769_I1_2_PIN);
133  MAX2769_I1_PORT(DIR) &= ~BV(MAX2769_I1_3_PIN);
134  MAX2769_I1_PORT(DIR) &= ~BV(MAX2769_I1_4_PIN);
135  MAX2769_I1_PORT(DIR) &= ~BV(MAX2769_I1_5_PIN);
136  MAX2769_I1_PORT(DIR) &= ~BV(MAX2769_I1_6_PIN);
137  MAX2769_I1_PORT(DIR) &= ~BV(MAX2769_I1_7_PIN);
138  MAX2769_I1_PORT(DIR) &= ~BV(MAX2769_I1_8_PIN);
139 }
140 
141 /*----------------------------------------------------------------------------*/
149 void SYS_GPS_InitControlIO(void)
150 {
151  // MAX2769 is in operation
152  MAX2769_SHDN_N_PORT(OUT) |= BV(MAX2769_SHDN_N_PIN);
153  MAX2769_SHDN_N_PORT(DIR) |= BV(MAX2769_SHDN_N_PIN);
154 
155  // MAX2769 is in operation
156  MAX2769_IDLE_N_PORT(OUT) |= BV(MAX2769_IDLE_N_PIN);
157  MAX2769_IDLE_N_PORT(DIR) |= BV(MAX2769_IDLE_N_PIN);
158 }
159 
160 /*----------------------------------------------------------------------------*/
168 void SYS_GPS_InitProgramIO(void)
169 {
170  // CLEON uses default device state 2 (PGM:1, CS:0, SCLK:0, SDATA:1)
171  // - IF: 4092000 Hz
172  // - Sampling rate: 16368 samples/sec
173  // - CMOS level I0 and I1
174 
175  // PGM pin is set to high
176  MAX2769_PGM_EN_N_PORT(OUT) |= BV(MAX2769_PGM_EN_N_PIN);
177  MAX2769_PGM_EN_N_PORT(DIR) |= BV(MAX2769_PGM_EN_N_PIN);
178 
179  // CS pin is set to low
180  MAX2769_PGM_CS_N_PORT(OUT) &= ~BV(MAX2769_PGM_CS_N_PIN);
181  MAX2769_PGM_CS_N_PORT(DIR) |= BV(MAX2769_PGM_CS_N_PIN);
182 
183  // SCLK pin is set to low
184  MAX2769_PGM_SCLK_PORT(OUT) &= ~BV(MAX2769_PGM_SCLK_PIN);
185  MAX2769_PGM_SCLK_PORT(DIR) |= BV(MAX2769_PGM_SCLK_PIN);
186 
187  // SDATA pin is set to high
188  MAX2769_PGM_SDATA_PORT(OUT) |= BV(MAX2769_PGM_SDATA_PIN);
189  MAX2769_PGM_SDATA_PORT(DIR) |= BV(MAX2769_PGM_SDATA_PIN);
190 }
191 
192 /*----------------------------------------------------------------------------*/
200 void SYS_GPS_StartOperation(void)
201 {
202  // LDO for GPS is turned on
203  GPS_PWR_SHDN_N_HIGH();
204 }
205 
206 /*----------------------------------------------------------------------------*/
214 void SYS_GPS_StopOperation(void)
215 {
216  // LDO for GPS is in shutdown mode
217  GPS_PWR_SHDN_N_LOW();
218 }
219 
220 /*----------------------------------------------------------------------------*/
228 bool SYS_GPS_TestGPS(unsigned int uiDelay)
229 {
230  unsigned int uiTestCountFor0xFF = 0;
231  unsigned int uiTestCountFor0x00 = 0;
232 
233  // Start GPS operation
234  SYS_GPS_StartOperation();
235 
236  // Allow GPS time to settle
237  SYS_GPS_TimingDealy(uiDelay);
238 
239  // Start DMA transfer
240  DMA0CTL |= DMAEN;
241 
242  // Wait until DMA transfer completed
243  while((DMA0CTL & DMAIFG) != DMAIFG);
244  DMA0CTL &= ~DMAIFG;
245 
246  // Count the number of '0xFF' and '0x00'
247  for(int i = 0 ; i < SIZE_OF_GPS_DATA_CHUNK_IN_BYTE ; i++ ){
248  if(uniCLEONGPSData.ucSignal[i] == 0xFF){
249  uiTestCountFor0xFF++;
250  }else if(uniCLEONGPSData.ucSignal[i] == 0x00){
251  uiTestCountFor0x00++;
252  }
253  }
254 
255  // Stop GPS operation
256  SYS_GPS_StopOperation();
257 
258  // If number of '0xFF' or '0x00' exceeds half or total sampled signal, regards GPS chip is not functional
259  // (number of '0xFF' or '0x00' cannot exceed half of captured GPS signal due to signal's physical nature)
260  if((uiTestCountFor0xFF > (SIZE_OF_GPS_DATA_CHUNK_IN_BYTE/2))||(uiTestCountFor0x00 > (SIZE_OF_GPS_DATA_CHUNK_IN_BYTE/2))){
261  return _FAIL_;
262  }else{
263  return _SUCCESS_;
264  }
265 }
266 
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